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download PDF document: pmc.sandybridgeuc.3.pdf

PMC.SANDYBRIDGEUC(3) FreeBSD Library Functions Manual PMC.SANDYBRIDGEUC(3)
NAME pmc.sandybridgeuc - uncore measurement events for Intel Sandy Bridge family CPUs
LIBRARY Performance Counters Library (libpmc, -lpmc)
SYNOPSIS #include <pmc.h>
DESCRIPTION Intel Sandy Bridge CPUs contain PMCs conforming to version 3 of the Intel performance measurement architecture. These CPUs contain two classes of PMCs:
PMC_CLASS_UCF Fixed-function counters that count only one hardware event per counter.
PMC_CLASS_UCP Programmable counters that may be configured to count one of a defined set of hardware events.
The number of PMCs available in each class and their widths need to be determined at run time by calling pmc_cpuinfo(3).
Intel Sandy Bridge PMCs are documented in Volume 3B: System Programming Guide, Part 2, Intel(R) 64 and IA-32 Architectures Software Developers Manual, Order Number: 253669-039US, Intel Corporation, May 2011.
SANDYBRIDGE UNCORE FIXED FUNCTION PMCS These PMCs and their supported events are documented in pmc.ucf(3). Not all CPUs in this family implement fixed-function counters.
SANDYBRIDGE UNCORE PROGRAMMABLE PMCS The programmable PMCs support the following capabilities:
Capability Support PMC_CAP_CASCADE No PMC_CAP_EDGE Yes PMC_CAP_INTERRUPT No PMC_CAP_INVERT Yes PMC_CAP_READ Yes PMC_CAP_PRECISE No PMC_CAP_SYSTEM No PMC_CAP_TAGGING No PMC_CAP_THRESHOLD Yes PMC_CAP_USER No PMC_CAP_WRITE Yes
Event Qualifiers Event specifiers for these PMCs support the following common qualifiers:
cmask=value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to value.
edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. qualifier.
Event Specifiers (Programmable PMCs) Sandy Bridge programmable PMCs support the following events:
CBO_XSNP_RESPONSE.RSPIHITI (Event 22H, Umask 01H) Snoop responses received from processor cores to requests initiated by this Cbox. Must combine with one of the umask values of 20H, 40H, 80H
CBO_XSNP_RESPONSE.RSPIHITFSE (Event 22H, Umask 02H) Must combine with one of the umask values of 20H, 40H, 80H
CBO_XSNP_RESPONSE.RSPSHITFSE (Event 22H, Umask 04H) Must combine with one of the umask values of 20H, 40H, 80H
CBO_XSNP_RESPONSE.RSPSFWDM (Event 22H, Umask 08H)
CBO_XSNP_RESPONSE.RSPIFWDM (Event 22H, Umask 01H)
CBO_XSNP_RESPONSE.AND_EXTERNAL (Event 22H, Umask 20H) Filter on cross-core snoops resulted in external snoop request. Must combine with at least one of 01H, 02H, 04H, 08H, 10H
CBO_XSNP_RESPONSE.AND_XCORE (Event 22H, Umask 40H) Filter on cross-core snoops resulted in core request. Must combine with at least one of 01H, 02H, 04H, 08H, 10H
CBO_XSNP_RESPONSE.AND_XCORE (Event 22H, Umask 80H) Filter on cross-core snoops resulted in LLC evictions. Must combine with at least one of 01H, 02H, 04H, 08H, 10H
CBO_CACHE_LOOKUP.M (Event 34H, Umask 01H) LLC lookup request that access cache and found line in M-state. Must combine with one of the umask values of 10H, 20H, 40H, 80H
CBO_CACHE_LOOKUP.E (Event 34H, Umask 02H) LLC lookup request that access cache and found line in E-state. Must combine with one of the umask values of 10H, 20H, 40H, 80H
CBO_CACHE_LOOKUP.S (Event 34H, Umask 04H) LLC lookup request that access cache and found line in S-state. Must combine with one of the umask values of 10H, 20H, 40H, 80H
CBO_CACHE_LOOKUP.I (Event 34H, Umask 08H) LLC lookup request that access cache and found line in I-state. Must combine with one of the umask values of 10H, 20H, 40H, 80H
cacheable write requests. Must combine with at least one of 01H, 02H, 04H, 08H
CBO_CACHE_LOOKUP.AND_EXTSNP (Event 34H, Umask 40H) Filter on external snoop requests. Must combine with at least one of 01H, 02H, 04H, 08H
CBO_CACHE_LOOKUP.AND_ANY (Event 34H, Umask 80H) Filter on any IRQ or IPQ initiated requests including uncacheable, noncoherent requests. Must combine with at least one of 01H, 02H, 04H, 08H
IMPH_CBO_TRK_OCCUPANCY.ALL (Event 80H, Umask 01H) Counts cycles weighted by the number of core-outgoing valid entries. Valid entries are between allocation to the first of IDIO or DRSO messages. Accounts for coherent and incoherent traffic. Counter 0 only
IMPH_CBO_TRK_REQUEST.ALL (Event 81H, Umask 01H) Counts the number of core-outgoing entries. Accounts for coherent and incoherent traffic.
IMPH_CBO_TRK_REQUEST.WRITES (Event 81H, Umask 20H) Counts the number of allocated write entries, include full, partial, and evictions.
IMPH_CBO_TRK_REQUEST.EVICTIONS (Event 81H, Umask 80H) Counts the number of evictions allocated.
IMPH_COH_TRK_OCCUPANCY.ALL (Event 83H, Umask 01H) Counts cycles weighted by the number of core-outgoing valid entries in the coherent tracker queue. Counter 0 only
IMPH_COH_TRK_REQUEST.ALL (Event 84H, Umask 01H) Counts the number of core-outgoing entries in the coherent tracker queue.
SEE ALSO pmc(3), pmc.atom(3), pmc.core(3), pmc.corei7(3), pmc.corei7uc(3), pmc.iaf(3), pmc.k7(3), pmc.k8(3), pmc.sandybridge(3), pmc.sandybridgexeon(3), pmc.soft(3), pmc.tsc(3), pmc.ucf(3), pmc.westmere(3), pmc.westmereuc(3), pmc_cpuinfo(3), pmclog(3), hwpmc(4)
HISTORY The pmc library first appeared in FreeBSD 6.0.
AUTHORS The Performance Counters Library (libpmc, -lpmc) library was written by Joseph Koshy <jkoshy@FreeBSD.org>. The support for the Sandy Bridge microarchitecture was added by Davide Italiano <davide@FreeBSD.org>.
FreeBSD 14.0-RELEASE-p11 October 19, 2012 FreeBSD 14.0-RELEASE-p11